Eswar Mahalingam · Digital Electronics & VLSI Intern · 10 projects, every number measured by the code in this repo (Icarus / GHDL / Yosys / nextpnr-ice40 / icetime)
4-way intersection FSM with pedestrian phase, debounced emergency override per approach with safe yellow→all-red hand-over, 1 Hz divider and 7-segment countdown.
| Checks | 39 / 39 |
| Safety assertions fired | 0 |
| iCE40 LCs | 318 / 7680 |
| Fmax (icetime) | 109.4 MHz |
Baseline vs low-power ALU (clock gating, operand isolation, one-hot decode) mapped to a CMOS std-cell library and gate-level simulated with identical stimulus.
| RTL ↔ gate match | 4 × 590/590 |
| Power baseline → LP | 390.8 → 141.3 µW |
| Reduction | −63.8 % |
| Area penalty | +0.2 % |
4×4 keypad scanner with debounce, 4-digit PIN FSM, change-PIN, 3-strike lockout with alarm and timeout, master reset, dual 7-segment status.
| Checks | 38 / 38 |
| Key presses simulated | 88 |
| iCE40 LCs | 439 |
| Fmax | 97.2 MHz |
15-tap Q1.15 low-pass FIR in direct, transposed and pipelined-symmetric forms; compared for area, speed and power on FPGA and CMOS flows.
| Bit-exact vs model | 3 / 3 |
| SNR vs float | 88.9 dB |
| Fmax D / T / S | 38.7 / 99.1 / 90.7 MHz |
| CMOS power D / T / S | 9.4 / 8.3 / 7.2 mW |
TX/RX FSMs with 16× oversampling, parity and stop-bit options, framing/parity/overflow flags, 8-deep RX FIFO, loopback top and PC terminal script.
| Frames / checks | 46 / 68 |
| Baud rates | 9600 · 115200 · 921600 |
| iCE40 LCs | 378 |
| Fmax | 135.0 MHz |
Verilog metering DSP (Vrms/Irms/P/Wh, imp/kWh pulse) + portable C firmware with SIM800L AT state machine (host-built, mocked) + Indian slab-tariff billing simulation.
| Registers bit-exact | 37 / 37 |
| Firmware host checks | 20 / 20 |
| iCE40 LCs | 2393 / 7680 |
| Fmax | 44.7 MHz |
Custom 16-opcode ISA, 4×4 register file, ALU with Z/C, 3-cycle FSM control unit, ROM/RAM, Python assembler and golden ISA simulator.
| Programs verified | 3 / 3 |
| Unit tests | 4 / 4 |
| iCE40 LCs | 317 |
| Fmax | 115.9 MHz |
Yosys synthesis → CMOS liberty → gate-level equivalence → own Python floorplan / annealing placement / maze routing / real GDSII writer; ORFS sky130 + KLayout configs shipped.
| RTL ↔ gate checksum | identical |
| HPWL after annealing | −47 % |
| Nets routed | 122 / 122 |
| DRC-lite violations | 0 |
Sensor blocks, relay interlock, PWM fan/RGB, register-mapped UART command interface for ESP8266/HC-05, clock-gated sleep controller with wake-on-PIR; bridge firmware + mock Wi-Fi bridge.
| Checks | 40 / 40 |
| Mock bridge replies | 16 / 16 |
| Dynamic power (sleep) | −23.6 % |
| Fmax | 43.3 MHz |
Debounced switches, officer-gated ballot FSM, I²C master writing CRC-8 sequenced records to a 24LC256 model with write-verify, tamper seal, PIN-gated results on 7-segment and HD44780 LCD.
| Checks | 32 / 32 |
| EEPROM records w/ valid CRC | 4 / 4 |
| iCE40 LCs | 1467 |
| Fmax | 88.3 MHz |